Executive Summary : | The growing number of devices connected to the internet, projected to reach 75 billion by 2025, presents opportunities for computing near data sources instead of relying on cloud networks. Intelligence can be embedded into edge computing devices through hardware implementation of deep learning (DL)/machine learning (ML) algorithms. However, edge computing requires specialized hardware architectures to overcome power, available on-chip memory, and small size constraints. Novel design methodologies can address these challenges by ensuring low latency, least power consumption, and high accuracy in AI-related task prediction. Obtaining these hardware architectures manually is challenging and ineffective. This project proposes a specification-guided automatic methodology for designing hardware architectures suitable for various edge computing applications, such as smart homes, in-hospital patient monitoring, point-of-care diagnostics, and automotive-related tasks. Learning algorithms, typically in the form of neural networks, are selected based on application specifications and optimized using pruning, quantization, and fusion. The hardware architecture is represented at multiple design abstraction levels using co-design techniques. Handling security is a major concern due to internet-connected devices and manufacturing designs in lower technology nodes. The project aims to develop an analytical framework for dependability and hardware security assessment of designs, incorporating suitable mechanisms and countermeasures to ensure hardware security and dependability for wide-scale deployment for multiple edge computing applications. The designed hardware architecture will be implemented using FPGA boards and demonstrated for specific edge computing applications. |