Executive Summary : | According to the guidelines of the International Roadmap for Devices and Systems (IRDS, 2021 Edition), the challenges with the scaling of conventional planar MOSFET enforces adoption of advanced devices such as nanowire field-effect-transistor, and nano-sheet FETs structures. These structures would be of great interest in coming years, in order to effectively scale the FETs to sub 5-nm gate length [1-3]. Since, many of the proposed structures are yet to be fabricated, it is suggested by the IRDS to investigate different physical aspects of such non- classical CMOS devices for their introduction and practical demonstration. GAA nanowires (NW) transistors have proved their efficiency over FinFETs for sub 10 nm technology nodes [1-4]. They enable extreme CMOS device scaling and pose finest electrostatic control as compared to FinFETs [2-4]. Moreover, the Gate-All-Around (GAA) stacked nanosheets tackle different design and fabrication intricacies related to FinFETs for the spot-on 5 nanometre node and beyond [4-5]. Nanosheet technology withstands beyond 25% boost in terms of performance, 50% additional power saving as compared to the currently available and crucial 7nm FinFET technology of the foundry. Moreover, nanosheet structure provides variable sheet width with more streamlined design as compared to FinFET [9-16]. A slight structural modification may further optimize power consumptions in nanosheet FETs. If the standard insulator in the gate-stack of FETs is substituted with a ferroelectric material of an apt thickness, it is feasible to realize a step-up voltage transformer in order to effectively raise the voltage at the gate terminal of a MOSFET. Such a set-up of gate and gate oxide introduces a new category of semiconductor FETs termed as the negative capacitance FET abbreviated as NCFET. In this device, the gate stack is operated in such a manner that permits to attain values of subthreshold swing (SS) lower than 60 mV/decade thereby allowing low voltage/power operation [14-16]. The present project proposal is to accomplish the modeling, TCAD simulations and optimization of various performance parameters of negative gate capacitance nanosheet FETs (NC-NS-FETs) with sub-10nm gate lengths. Since the SS and leakage current are of special importance to determine the switching characteristics and power consumption of these devices, therefore, detailed investigation using simulation and modeling is needed to study terminal behavior of these devices for various applications. The diverse design attributes centered on device performance optimization will be inspected using both the analytical models and TCAD simulations in this project. The study will also deal with different design aspects based on performance optimization using three dimensional (3-D) TCAD simulation approach. |