Executive Summary : | The emergence of the Internet-of-Things (IoT), and cloud computing have led to the need for a semiconductor memory with low cost, high performance, high density (less chip area), low power dissipation, and better reliability. Among, them dynamic random access memory (DRAM) has gained tremendous attention due to its inherent simple structure and dominance in the memory market. While we have seen exponential growth in the number of DRAM memory cells per chip, the DRAM scaling has reached its bottleneck due to the capacitor which has become harder to scale, as MOSFET geometries scale. In addition, the radiation-induced single event upset (SEU) has become a serious concern for cloud computing and memory systems these days. When these memories are used in space applications, they suffer from reliability problems due to their exposure to the heavy energy charged particles and cosmic rays. This may result in soft error issues in memory and can corrupt the information stored in the memory. The abnormal function of electronic devices can lead to catastrophic accidents of spacecraft. Also, it has been reported that with technology node and supply voltage scaling the SEU may increase more than 5%, which can further pose some major reliability concerns. Therefore, in this research proposal we have focused on two major problems: (a) DRAM scaling challenges and (b) investigation of radiation-induced single event upset on DRAM device and memory array. To overcome, the DRAM scaling issues researchers have proposed several new devices and materials. Among, them single transistor DRAM has attracted considerable attention due to its simple fabrication flow. Therefore, to surpass the conventional DRAM scaling challenge we have proposed a new Bipolar Impact Ionization MOS (I-MOS) based single transistor DRAM. The proposed single transistor DRAM uses the internal current gain mechanism of the parasitic BJT in a MOSFET to initiate the impact ionization at a lower supply voltage than the conventional I-MOS. The hysteresis in the output characteristics of the Bipolar I-MOS makes this device useful for realizing single transistor DRAM. The proposed single transistor DRAM shows ~ 5x higher retention time than the ITRS spec at 358K. In addition, the proposed single transistor DRAM also exhibits non-destructive read operation and higher endurance. Furthermore, to investigate the radiation-induced SEU due to heavy ion irradiation on a single transistor DRAM we have used the device-circuit co-simulation approach. For this, we have developed a look-up table-based Verilog-A model. The Verilog-A model is generated from TCAD simulation data. In addition, to study the radiation-induced SEU on a single transistor DRAM memory array we have developed the 3x3 array and studied the performance under various conditions. Therefore, this research project will pave the way for designing future main memory using single transistor DRAM under the heavy ion irradiation environment. |