Executive Summary : | To keep the form factor of the RF circuit small, there is keen interest in the moving from traditional heterodyne receiver to direct RF-sampling receiver, which samples the received RF signal directly using an RF analog to digital converters (ADC). A very low jitter clock is required for such ADC to prevent the channel mixing as per the Nyquist criterion. The demand for the higher and higher data rate for both the wired and wireless communication is increasing even at faster rate. To meet this ever increasing higher data rate requirement, the newly launched 5G new radio (NR) communication is using higher-order modulation of 256 quadrature-amplitude-modulation (QAM) leading to data rate of 10 Giga bit per second (Gbps) or more. Such higher modulation requires a low integrated phase noise (IPN) of -37 dBc or less, which means around 370 fs of jitter for 6 GHz. To get even higher data rate of 30 Gbps or more, the next generation wireless local area network standard IEEE 802.11be, which is also known as Wi-Fi 7, has been proposed. This standard is going to use 4096 QAM, along with MIMO, technique to achieve such a high data rate. To satisfy very strict error vector magnitude (EVM) requirement of these emerging communication standards, local oscillator with an ultra-low jitter of less than 100 fs is needed. In the wired communication also e.g. multi gigabit transmission (MGT) which is a serializer and deserializer (SerDes) operating at more than 1 Gbps, a very low jitter clock is mandatory. In this project, CMOS integrated circuits will be designed and fabricated to meet the above mentioned requirements. Various ideas which will be used to create the IC, will be based on Injection-locked frequency multiplier, Sub-sampling phase locked loop, bang-bang fractional-N phase locked loop. A cascade of the above mentioned circuits will be used especially for producing mmWave frequency. |