Research

Astronomy & Space Sciences

Title :

Design of PLL with VCO, 40MHz -1000MHz, Ultra low phase noise -110dBc/Hz, very low RMS jitter<180fs

Area of research :

Astronomy & Space Sciences

Focus area :

VLSI Design

Contact info :

Details

Executive Summary :

The aim is to design a PLL which could beused in various circuits as embedded blockand as standalone device.The PLL must generate clock rates in therange 40 –1000 MHz range with very low RMS jitter.

Co-PI:

HS Jatana, Semi Conductor Laboratory (SCL), Chandigarh, Ashutosh Yadav, Semi Conductor Laboratory (SCL), Chandigarh

Organizations involved