Executive Summary : | Neuromorphic computing aims to bridge the incompatibility between artificial intelligence and hardware infrastructure by mimicking synaptic and neuronal behavior. Autonomous spiking neural networks (SNNs) using sparse, asynchronous voltage pulses are promising candidates for edge computing applications. However, achieving a CMOS-compatible device with tunable synaptic plasticity remains a major challenge. Biologically inspired iontronic transistors and conductive bridge memristors rely on the movement of ionic species to emulate synaptic plasticity, but these implementations violate stringent CMOS foundry processes. To address this challenge, an ultra-thin 2D channel with enhanced sensitivity towards charge trapping dynamics is being explored. However, the precise origin of charge trapping dynamics and the ability to tune synaptic plasticity remains elusive. This proposal proposes a dual-gated MoS₂ transistor to achieve tunable synaptic properties. The pristine bottom gate (HfO₂) will apply synaptic spikes, while the defective top gate dielectric (Si₃N₄) will tune electron trap density and associated time constants. The project aims to understand the charge trapping mechanism in a dual-gated MoS2 Schottky barrier transistor by building a TCAD model and calibrating it with experimental data and electrical measurements. The second stage involves CMOS compatible nanofabrication and electrical characterization of the proposed device, aiming to experimentally ascertain the influence of the top gate on tuning the trapped charge density, time constants, and synaptic plasticity parameters. This work addresses two key technological challenges in the area of 2D materials-based neuromorphic devices. The calibrated TCAD model will reveal key interfaces governing charge trapping dynamics in a 2D channel transistor, and the project demonstrates the ability to control charge trapping dynamics and synaptic plasticity in a CMOS compatible device. |