Executive Summary : | In this project, we will work on Magneto electric spin orbit (MESO) Logic for the energy efficient beyond CMOS computing applications. The new multiferroic based MESO logic is expected to overcome the difficulties of current technologies faced by the CMOS devices namely, high power consumptions, reaching moore’s law limit to scale down, etc. The MESO logic is constructed using the ferromagnetic (FM) free layer, multiferroic layer (ML) with high magnetoelectric effect, topological insulating (TI) layer with high spin orbit coupling. Owing to its promise toward the minimizing the power requirements (induce power-efficient magnetization switching of the FM layer), MESO devices attracted the attention of the researchers worldwide. These are perfect candidates to replace the CMOS technology for the further scaling down following the moore’s law. Though these devices are promising, in order to commercial the MESO devices, lot of properties need to be improved. This proposal is mainly focusing in addressing the challenges in designing the MESO devices by the choice of suitable material selections. In this project, we will prepare novel multilayer stacks that comprise the TI and FM and ML layers along with the seed layer. The stacks’ structure is Si/SiO2/seed layer/ML/TI/FM. By varying the thickness, a systematic investigation will be performed for the power-efficient and field-free switching of magnetization of the middle ML layer with perpendicular magnetic anisotropy (PMA) in these stacks. The TI layer with high spin orbit coupling provides the power efficient magnetization while the Multiferroic Layer with in-plane magnetic anisotropy (IMA) minimizes the external magnetic field requirements and provides the field free switching. The TI and ML targets will be prepared initially with high structural purity and the corresponding thin films will be deposited using the RF Sputtering. Then, we will investigate for the structural properties and the thickness will be measured using the x-ray reflectivity. The electric and magnetic measurements swill be performed for the optimization of the properties with respect to the thickness. The device will be made using the Photo Lithography and it will be investigated for the input power and corresponding output voltages will be recorded to check the power efficiency. The successful completion of the project not only lifts the challenges of CMOS technology, gives a road map for the new devices towards the commercialization. Besides, the research will be published in high impact journals and the results will be presented in the national and international conferences. |