Astronomy & Space Sciences
Title : | Modeling of high voltage (10-20, 40-60V) N /P LDMOS devices developed at SCL in 180nm CMOS baseline process technology |
Area of research : | Astronomy & Space Sciences |
Focus area : | Semiconductor Device Modeling |
Details
Executive Summary : | Process development work at SCL is inprogress for the process integration of LDMOS(VDS: 10-20, 40-60V; VGS: 3.3-5V) devices (nand PMOS) in standard 180nm baselineprocess. Once the devices are enabled, SPICE device models are required for theabove LDMOS devices for circuit designimplementation. The developed models shouldbe accurately predicting both DC and ACperformance of the devices over a range ofvoltage, temperatures (-55 to 125°C) andfrequencies. |
Co-PI: | Shri Amit Kumar Singh, Semi Conductor Laboratory (SCL), Chandigarh, Shri Saahil Singla, Semi Conductor Laboratory (SCL), Chandigarh |
Organizations involved
