Astronomy & Space Sciences
Title : | Design of PLL with VCO, 40MHz -1000MHz, Ultra low phase noise -110dBc/Hz, very low RMS jitter<180fs |
Area of Research : | Astronomy & Space Sciences |
Focus Area : | VLSI Design |
Co-PI: | HS Jatana, Semi Conductor Laboratory (SCL), Chandigarh, Ashutosh Yadav, Semi Conductor Laboratory (SCL), Chandigarh |
Contact info : | gh_dpg@scl.gov.in |
Details
Executive Summary : | The aim is to design a PLL which could beused in various circuits as embedded blockand as standalone device.The PLL must generate clock rates in therange 40 –1000 MHz range with very low RMS jitter. |
Organizations involved